Dynamic random access memory (DRAM) often includes a memory cell, including a memory capacitor, and a transistor connected with the memory capacitor. The memory capacitor is used to store data; and the transistor is used to control the data storage of the memory capacitor.
The working mechanism of the DRAM is as the following. The word line of the DRAM is electrically connected to the gate of the transistor in the memory cell to control the “on/off” of the transistor. The source of the DRAM is electrically connected to the source of the transistor to form a current transport path. The drain of the transistor is connected to the memory base substrate to store and/or output data.
Currently, in the commonly used DRAM, the memory capacitor is often designed to be a trench capacitor, or a stacked capacitor. The trench capacitor is buried in a semiconductor substrate. The stacked transistor is stacked on a semiconductor substrate.
However, the fabrication process of the existing DRAM is complicated. The disclosed methods and structures are directed to solve one or more problems set forth above and other problems in the art.